1. Field of the Invention
The present invention relates to an information processing apparatus equipped with a plurality of CPUs and to a method of controlling this apparatus.
2. Description of the Related Art
A non-volatile memory typified by a flash memory is available as a memory device used in an information processing apparatus. Since a non-volatile memory is capable of retaining stored data even if the supply of electric power thereto is interrupted, such a memory is used to deal with an unexpected electric power interruption in built-in devices.
The specification of Japanese Patent Laid-Open No. 2001-147855 describes an invention in which a cache is applied in a main memory. Further, the specification of Japanese Patent Laid-Open No. 7-244614 describes a technique in which, in a unit having a buffer with a high access speed, a non-volatile memory with a low access speed and a controller, data that has been stored in the non-volatile memory having the low access speed is cached in the buffer having the high access speed, whereby the data that has been stored in the non-volatile memory can be read out at high speed.
However, in a case where an apparatus has first and second CPUs and is controlled by an operating system in which the first CPU manages a virtual memory area, the second CPU cannot access the virtual memory area directly. Consequently, in a case where the operating system executed by the first CPU uses the virtual memory area, a situation arises in which the second CPU cannot transfer data to the cache area defined by the first CPU.